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PEOPLE / EXPERTISES
김견수공학박사/대표변리사

학력 및 자격

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  • 부산대학교 전자공학과 박사

  • 미국 University of Southern California, Viterbi School of Engineering, Post-Doc.

     (Asynchronous CAD/VLSI 그룹)

  • 47회 변리사 시험 합격

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경력
 

  • 다함특허법률사무소 대표변리사

  • 특허청 책임 심사관(MPEG 비디오, 영상기기, 컴퓨터 발명, 방송 분야 심사)

  • 일륭텔레시스(주) 연구소장(ADSL/VDSL, DVR(4/9/16 채널 MJPEG/MPEG-2-based) 개발)

  • KT 연구개발원 연구원(지능망/신호망교환기/MPEG-2 비디오 코덱/비동기식 VLSI 시스템 개발)

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주요 IP 컨설팅 실적

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  • 표준과 특허, 특허 풀 - MPEG-4 특허 현황 및 대응방안 (전자산업진흥회, 2007)

  • 멀티 제스처와 터치스크린패널 구조 관련 특허분석 (삼성전기, 2012)

  • 스마트의료정보 EHR, PHR 및 원격의료시스템 표준문서/표준특허 조사분석 사업 (기술표준원, 2012 ~ 2013)

  • R&D 표준특허창출사업-TPEG 국제표준화 및 IPR 확보방안 연구 (2012, TPEG 포럼 코리아)

  • 지재권중심의 기술획득전략 사업-차세대 OLED 증착장비 (R&D 특허센터, 2012)

  • 융복합반도체 분야 표준특허 확보 및 표준화 연계 방안 도출 과제 수행 (2014, 기술표준원)

  • 스마트의료정보 특허조사사업 수행 - 1) EHR 분야, 2) PHR 분야, 3) 모바일 헬스 분야, 4) 바이오 헬스 분야, 5) 스마트 헬스 데이터 분야 수행 (기술표준원/한국표준협회, 2013)

  • R&D 표준특허창출사업-OFDMA기반 10Gbyte/s급 광링크 및 유무선 융합액세스 네트워크 기술 개발 (특허정보진흥센터, 2013)

  • IP R&D 전략특화과제-환경외력을 반영한 부유식  풍력 발전기용 블레이드 건전성 모니터링 및 개별 피치 예측제어 (지식재산전략원, 2013)

  • IP R&D 전략수립과제-온오프 스위치 디밍 (지식재산전략원, 2014)

  • IP R&D 지재권 과제-수출용 10G EPON (지식재산전략원, 2015)

  • 표준특허창출사업-국제표준기반 딥러닝 기반 힐링플랫폼 표준특허 및 표준화 전략 개발 (지식재산전략원, 2015)

  • 딥러닝 기계학습에 기반한 건강정보 유사사례검색 관련 표준특허 창출 사업 수행 (지식재산전략원, 2016)

  • 앙상블 딥러닝 기반 Clinical Decision Support System 과제 수행 (2016)

  • 글로벌 기술혁신 IP 전략개발사업-DPoE(DOCSIS Provision over EPON) (지식재산전략원, 2016)

  • 시스벨 10G-EPON-WiFi 특허분쟁 대응전략 사업 (지식재산보호원, 2016)

  • IP기반 UHD급 비디오 라우팅 스위처/Video over IP 관련 특허 조사/분석 및 신규특허 창출사업 – (2015~2016)

  • IP 기반 멀티카메라 영상 촬영 시스템 신규특허 창출 사업 (2017)

  • 공진식 무선 전력 전송 시스템 신규특허 창출사업 (2017)

  • 5G 통합 액세스 솔루션 IP-R&D 특허 창출사업 - G.hn Coaxial/5G Virtualization, Network Slice, SDN Orchestration (2017)

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R&D 실적

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  • 지능망/신호망 교환기 및 관리 시스템

  • MPEG-2 비디오 코덱 칩 개발

  • 비동기식 VLSI 시스템 개발

  • 통신장비개발(ADSL, VDSL, DSLAM)

  • MJPEG/MPEG 기반 DVR 개발

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자문/수상 실적

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  • MPEG 비디오 코덱 표준특허 심사 및 자문

  • ISO/IEC 13818-2 표준 기고문 검토

  • 일체형터치 사업관련 국내외 특허분석 및 분쟁사례와 국내업계의 대응전략 강사(산업교육연구소, 2011~2013)

  • 검색최우수 심사관, 특허심사 우수심사관(특허청)

  • 컴퓨터발명심사기준/PCT 매뉴얼/특허 실용신안 심사지침서 개정위원(특허청)

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​특허 등록

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  1. KR 2000-0039397 A 20000705 1998-0054716 19981212 발신자의 전화번호와 영상이 저장 가능한 영상 전화기 (The video phone in which the telephone number and image of the originator can be stored)

  2. KR 1999-0086737 A 19991215 1998-0019863 19980529 비동기식 선입선출 시스템의 제어 장치 (The control device of the asynchronous method FIFO system)

  3. KR 1999-0085934 A 19991215 1998-0018637 19980522 비디오 인코더의 인터페이스 장치 (The interface equipment of the video encoder)

  4. KR 808786 B1 20080222 2000-0052615 20000906 다중채널/다중레벨을 이용한 동작감지 장치 및 그 방법 (Apparatuses and Methods for Motion Detection using Multi-Channel/Multi-Level)

  5. KR 748341 B1 20070803 2000-0072966 20001204 다중채널/다중레벨 동작감지기를 이용한 감시 시스템 및그 방법 (Methods and Apparatuses for Monitoring System using Multi-Channel/Multi-Level Motion Detector)

  6. KR 731492 B1 20070615 2000-0072967 20001204 다중채널/다중레벨 동작감지기능을 가지는 비디오 부호기 및 그 동작 감지 방법 (Apparatuses for Video Encoder having the Functions of Multi-Channel/Multi-Level Motion Detection and Motion Detection Method)

  7. KR 707669 B1 20070406 2000-0072854 20001204 동작 감지 기능을 가지는 비디오 부호화기 및 그를 이용한 동작 감지 방법 (Apparatus and Method for Motion detectable Video Encoder)

  8. KR 668211 B1 20070105 1999-0060281 19991222 통계적인 최적화를 이용한 비동기식 멀티레벨 배럴쉬프터 (ASYNCHRONOUS MULTI-LEVEL BARREL SHIFTER USING STATISTICAL OPTIMIZATION)

  9. KR 655573 B1 20061201 2000-0069414 20001122 동작 감지 기능을 이용한 멀티미디어 메일 서비스 시스템및 그 방법 (Multimedia mail service system and method using motion detection)

  10. KR 616222 B1 20060818 1999-0060271 19991222 데이터에 의해 구동되는 도미노 회로 (DATA DRIVEN DOMINO CIRCUIT)

  11. KR 586599 B1 20060526 1999-0067965 19991231 이산여현변환을 위한 비동기식 매트릭스-벡터 곱셈기 (asynchronous matrix-vetcor multiplier for discrete cosine transform)

  12. KR 580101 B1 20060508 1999-0060266 19991222 최상위비트에 의해 제어되는 버스 인버트 코딩 및 디코딩방법과 그 장치 (BUS INVERT CODING/DECODING METHOD AND DEVICE CONTROLLED MOST SIGNIFICANT BIT)

  13. KR 333745 B1 20020410 1998-0060149 19981229 부호화영상데이터인터페이스 장치 및 그 방법 (Interface apparatus and method of coding image data)

  14. KR 322485 B1 20020116 2001-0040043 20010705 다중채널 영상신호 부호화 장치 및 그 방법 (Multi-Channel Video Encoding apparatus and method thereof)

  15. KR 312420 B1 20011009 1998-0054715 19981212 역방향재생을 용이하게하기 위한 동영상부호화 방법 (Video code method for esay reverse video play)

  16. KR 312420 B1 20011009 1998-0054715 19981212 역방향재생을 용이하게하기 위한 동영상부호화 방법 (Video code method for esay reverse video play)

  17. KR 291480 B1 20010313 1997-0081255 19971231 4:2:2포멧영상의 4:2:0포멧변환 장치 (4:2:0 apparatus for converting format image of 4:2:2 format image)

  18. KR 289621 B1 20010221 1998-0060152 19981229 비디오 인코더의 변환 및 역변환 부호화 장치 및 그 방법 (The conversion of the video encoder and reverse conversion coding equipment and method thereof)

  19. KR 288142 B1 20010205 1998-0060153 19981229 부호화 영상 데이터의 인터페이스 장치 및 그 방법 (The interface equipment and method thereof of coding image data)

  20. KR 283088 B1 20001205 1998-0061636 19981230 비동기식 가변길이 복호장치 (The asynchronous method variable length decoder apparatus)

  21. KR 281575 B1 20001118 1998-0054722 19981212 모르스 부호를 인식할 수 있는 이동 단말기 (The mobile terminal recognizing clearly the morse code)

  22. KR 281567 B1 20001118 1998-0014524 19980423 비디오 인코더의 스케쥴링 방법 (The scheduling method of the video encoder)

  23. KR 267374 B1 20000704 1997-0075691 19971227 후단 1차원 이산여현변환(DCT) 동작제어를 통한 전력소모를절감시키는 2차원 이산여현변환기(DCT) (2-d DCT saving the power consumption through the backend 1-d DCT operation control (DCT))

  24. KR 248085 B1 19991215 1998-0006283 19980226 영상 관련 데이터를 저장하기 위한 메모리 맵 구조를 가지는 에스디램 (The SD-RAM having the memory map structure for image related data being stored)

  25. KR 237885 B1 19991012 1997-0077370 19971229 비디오 압축 부호화에서 2차원 이산여현변환기(DCT)의 동작제어기 (The operation controller of 2-d DCT in the video compression encoder)

  26. KR 223051 B1 19990708 1996-0080016 19961231 MPEG-2 영상압축을 위한 가변장 부호화 장치의제어장치 (The varactor length coding apparatus subject apparatus for the mpeg-2 image compression)

  27. KR 223050 B1 19990708 1996-0080015 19961231 MPEG-2 영상압축장치용 헤더정보 가변장 부호화 장치 (The header information varactor length coding apparatus for the mpeg-2 image compression apparatus)

  28. KR 223049 B1 19990708 1996-0080014 19961231 MPEG-2 영상압축장치용 제어정보 가변장 부호화 장치 (The control information varactor length coding apparatus for the mpeg-2 image compression apparatus)

  29. KR 209357 B1 19990421 1996-0046489 19961017 MPEG-1 및 MPEG-2 비디오 역양자기 회로 (The MPEG-1 and MPEG-2 video inverse quantizer circuit)

  30. KR 202307 B1 19990319 1996-0080013 19961231 MPEG-2 영상압축을 위한 DCT 계수 가변장 부호화장치 (The DCT coefficient varactor length coding apparatus for the mpeg-2 image compression)

  31. KR 202306 B1 19990319 1996-0080012 19961231 MPEG-2 영상압축장치용 움직임정보 가변장 부호화 장치 (The motion information varactor length coding apparatus for the mpeg-2 image compression apparatus)

  32. KR 202305 B1 19990319 1996-0080011 19961231 엠피이지-2 영상압축장치용 가변장 부호화 장치 (The varactor length coding apparatus for the moving picture experts group -2 image compression apparatus)

  33. KR 194282 B1 19990208 1996-0039645 19960913 정확도 보상기를 이용한 이산 코사인 변환 방법 및 그 장치 (The discrete cosine transform method using the compensator the accuracy and apparatus thereof)

  34. KR 179497 B1 19981127 1995-0023941 19950803 지그재그 및 얼터네이트 주사변환회로 (The zigzag and alternate scan conversion circuit)

  35. KR 175733 B1 19981111 1995-0039153 19951101 비트-시리얼 메트릭스 전치를 위한 초대규모 집적회로 (The super large scale integration for the bit-serial metrics transpose)

  36. KR 110374 B1 19970109 1993-0014783 19930730 신호망 분석을 위한 그래픽 처리 방법 (The graphic processing method for the signal network analysis)

  37. KR 96244 B1 19960227 1993-0012861 19930708 신호망의 중앙 집중적 감시를 위한 그래픽 화면 개발 및 감시 방법 (The graphic screen development for the monitoring of the signal network and monitoring method central)

  38. US 2003-0016753 A1 20030123 2002-189183 20020705 Multi-channel video encoding apparatus and method

  39. GB 2306716 B  2000.02.16 1996-022841 1996.11.01 Performing bit-serial matrix transposition operations

  40. JP 2871610 B2 1999.01.08 1996-205848 1996.08.05 지그재그 및 아르타네이트 주사 변환 회로

  41. US 5805476 A  1998.09.08 1996-742342 1996.11.01 Very large scale integrated circuit for performing bit-serial matrix transposition operation

  42. US 5754232 A  1998.05.19 1996-689252 1996.08.05 Zig-zag and alternate scan conversion circuit for encoding/decoding videos

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논문 실적(Searched by google)

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https://www.researchgate.net/scientific-contributions/8010911_Kyeounsoo_Kim

Kyeounsoo Kim's scientific contributionswhile affiliated with University of Southern California, Los Angeles, CA, United States and other institutions. Selected papers listed herewith:

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1. Kyeounsoo Kim, P.A. Beerel, “A low-power matrix transposer using MSB-controlled inversion coding”, The First IEEE Asia Pacific Conference on ASICs, 1999. AP-ASIC '99.

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Abstract: This paper proposes a low-overhead MSB-controlled inversion coding technique to reduce the transition activity in a matrix transposer a commonly used component in 2-dimensional discrete cosine transform (DCT) and inverse DCT (IDCT) applications. A family of designs is identified in which this technique is applied to different bit slices of the matrix data and the optimal design within the family is determined using transition activity analysis driven by real image sequences. Our results suggest that the optimal design using MSB-controlled inversion coding yields power savings of 33% for DCT data and 46% for IDCT data. These results are remarkable since existing bus-invert coding techniques have high overheads and are only effective for system-level high-capacitive buses.

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2. Kyeounsoo Kim, P.A. Beerel, “A high-performance low-power asynchronous matrix-vector multiplier for discrete cosine transform”, The First IEEE Asia Pacific Conference on ASICs, 1999. AP-ASIC '99.

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Abstract: This paper proposes a high-performance low-power asynchronous architecture for matrix-vector multipliers of a constant matrix by a vector which are typically used in discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) applications. The architecture takes advantage of the statistics of DCT and IDCT data that suggest that the input data have mostly zero or small values. It avoids unnecessary arithmetic operations by quickly terminating multiplication by zero and significantly reduces power and delay when operating on a small-valued data by adaptively controlling effective word lengths using fine-grain bit-partitioning and speculative completion sensing.

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3. Kyeounsoo Kim · Jong-Seog Koh · Ki-Bum Suh · Jong-Wha Chong, “An efficient frame memory interface of MPEG-2 video encoder ASIC chip”, 1999. ICCE. International Conference on Consumer Electronics.

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Abstract: In this paper an efficient frame memory interface of an MPEG-2 video encoder is presented. The proposed architecture takes about 58% less hardware area than the existing architecture (Kim et al. 1997), and results in reducing the total hardware area of the video encoder up to 24.3%.

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4. P.A. Beerel, Sangyun Kim, Pei-Chuan Yeh, Kyeounsoo Kim, “Statistically optimized asynchronous barrel shifters for variable length codecs”, 1999. Proceedings. 1999 International Symposium on Low Power Electronics and Design.

 

Abstract: This paper presents low-power asynchronous barrel shifters for variable length encoders and decoders useful in portable applications using multimedia standards. Our approach is to create multi-level asynchronous barrel shifters optimized for the skewed shift control statistics often found in these codecs. For common shifts, data passes through one level, whereas for rare shifts, data passes though multiple levels. We compare our optimized designs with the straight-forward asynchronous and synchronous designs. Both pre- and post-layout HSPICE simulation results indicate that, compared to their synchronous counterparts, our designs provide over a 40% savings in average energy consumption for a given average performance. 

 

5. Kyeounsoo Kim, Jong-Seog Koh, “An area efficient DCT architecture for MPEG-2 video encoder”, IEEE Transactions on Consumer Electronics, Mar 1999.

 

Abstract: This paper presents an area efficient VLSI architecture of transform coding module for MPEG-2 video encoder. This module consists of 2-D DCT and 2-D IDCT, Q and IQ, and zigzag and alternate scan conversion circuits. Hardware cost and performance of this module are mainly affected by the 2-D DCT and 2-D IDCT. In the proposed architecture, it is shown that a single 1-D DCT/IDCT could take the roles of the 2-D DCT and 2-D IDCT. It is capable of reusing a single 1-D DCT/IDCT four times. It is based on the row-column decomposition technique. It can be achieved through precise timing schedules. Intuitively, three 1-D DCT/IDCT and a matrix transposition memory could be saved as compared to the conventional architectures, which usually use two one-dimensional transforms and transposition memory. Even though there are some extra circuits due to timing controls and processing sequence schedules, this architecture takes about 24% and 50% respectively less area than the architectures published by Miyazaki et al. (1993) and by Matsiu et al. (1994). This design and implementation are applicable to the MPEG-2 video encoder accepting NTSC and PAL image formats in which the number of clocks to be allocated during a macro block period is 1320 for 54 MHz operating clock. To reduce its processing time, the proposed architecture uses a 3-bit serial distributed arithmetic method. As a result, this architecture can be characterized to maximize the utilization of the hardware resources, end can be used for encoders having a similar structure as the MPEC-2 video encoder. It also can be applied to the ASIC chips for multimedia services especially requiring low hardware complexity.

 

6. Kibum Suh, Kyung Yuk Min, Kyeounsoo Kim, Jong-Seog Koh, Jong-Wha Chong, “A design of DPCM hybrid coding loop using single 1-D DCT in MPEG-2 video encoder”, Proceedings of the 1999 IEEE International Symposium on Circuits and Systems.

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Abstract: In this paper, a VLSI architecture for DPCM Hybrid Coding Loop (DHCL), which consists of 2D-DCT, quantization, scan conversion, inverse quantization and 2D-IDCT, is presented. The architecture of the DHCL is designed to handle macroblock data within 1320 cycles and suitable for MPEG-2 video encoder accepting NTSC and PAL image formats. Only single 1-D DCT/IDCT is used for the design instead of 2-D DCT and IDCT to reduce the hardware size, and 3-bit serial distributed arithmetic architecture is adopted for 1-D IDCT to reduce the processing time in this architecture. As the result, the maximum utilization of hardware can be achieved, and power consumption can be minimized. The proposed designs can be operated on 80 MHz clock. The area is 50% smaller than the previous methods with 2D-DCT and IDCT. The experimental results show that the accuracy of DCT and IDCT meet the IEEE specification.

 

7. Kyeounsoo Kim, Peter A. Beerel, “MSB-Controlled Inversion Coding for a LowPower Matrix Transposer”, IEE Electronics Letters, Oct 1999.

 

Abstract: The increasing demand for portable and wireless multimedia applications that rely on limited battery energy has made low power architectures and designs for these applications critical. Since real-time matrix transposition consumes a large fraction of the power in multi-dimensional image and signal processing, low-power matrix transposers are particularly important.

 

8. Kyeounsoo Kim, Peter A. Beerel, Youpyo Hong, “An asynchronous matrix-vector multiplier for discrete cosine transform”, Proceedings of the 2000 International Symposium on Low Power Electronics and Design.

 

Abstract: This paper proposes an efficient asynchronous hardwired matrix-vector multiplier for the two-dimensional discrete cosine transform and inverse discrete cosine transform (DCT/IDCT). The design achieves low power and high performance by taking advantage of the typically large fraction of zero and small-valued data in DCT and IDCT applications. In particular, it skips multiplication by zero and dynamically activates/deactivates required bit-slices of fine-grain bit-partitioned adders using simplified, static-logic-based speculative completion sensing. The results extracted by both bit-level analysis and HSPICE simulations indicate significant improvements compared to traditional designs.

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9. Sunan Tugsinavisut, Youpyo Hong, Daewook Kim, Kyeounsoo Kim,·Peter A. Beerel, “Efficient asynchronous bundled-data pipelines for DCT matrix-vector multiplication”, IEEE Transactions on VLSI Systems, May 2005.

 

Abstract: This paper demonstrates the design of efficient asynchronous bundled-data pipelines for the matrix-vector multiplication core of discrete cosine transforms (DCTs). The architecture is optimized for both zero and small-valued data, typical in DCT applications, yielding both high average performance and low average power. The proposed bundled-data pipelines include novel data-dependent delay lines with integrated control circuitry to efficiently implement speculative completion sensing. The control circuits are based on a novel control-circuit template that simplifies the design of such nonlinear pipelines. Extensive post-layout back-end timing analysis was performed to gain confidence in the timing margins as well as to quantify performance and energy. Comparison with a synchronous counterpart suggests that our best asynchronous design yields 30% higher average throughput with negligible energy overhead.

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